There has been renewed interest in MRAM memories due to the development of Magnetic Tunnel Junctions (MTJs) which have high magnetoresistance at ambient temperature. These magnetic random-access memories have many significant advantages:                speed comparable to that of SRAM (read and write operations take a few nanoseconds),        density comparable to that of DRAM,        non volatile, like FLASH memory,        no read/write fatigue,        insensitive to ionising radiation, a problem which is becoming increasingly acute due to the reduced dimensions of elementary transistors.        
This being so, they are increasingly replacing memory that uses more conventional technology based on the charge state of a capacitor (DRAM, SRAM, FLASH) and are becoming a universal memory.
The first magnetic memories that were produced consisted of a number of storage cells each consisting of an element having so-called “giant magnetoresistance” and consisting of a stack of several alternatively magnetic and non-magnetic metallic layers.
A description of this type of structure can be found, for example, in Documents U.S. Pat. No. 4,949,039 and U.S. Pat. No. 5,159,513 which deal with the basic structure and in Document U.S. Pat. No. 5,343,422 which deals with implementation of a random-access memory (RAM) based on these basic structures.
Because of its architecture, this technology makes it possible to produce non-volatile memories using technology that is simple but which has a limited capacity. The fact that the storage cells are connected in series along each line limits possible integration because the signal becomes weaker and weaker as the number of cells increases.
The development of Magnetic Tunnel Junction (MTJ) storage cells has made it possible to achieve significant improvement in the performance and method of functioning of these memories. Such magnetic tunnel junction memories are described, for instance, in Document U.S. Pat. No. 5,640,343. In their simplest forms, they comprise two magnetic layers of different coercivity separated by a thin insulating layer. When the magnetizations of the storage and reference layers respectively which constitute the above-mentioned magnetic layers located either side of the tunnel barrier are antiparallel, the resistance of the magnetic tunnel junction is high. Conversely, when the magnetizations are parallel, this resistance becomes low.
These two magnetic layers are preferably based on 3d metals (Fe, Co, Ni) and alloys thereof (likely to contain boron or zirconium so as to make the structure of said layers amorphous and flatten their interfaces) and the insulating layer conventionally consists of amorphous alumina (AlOx) or crystalline magnesium oxide (MgO). Advantageously, the reference layer, which is also referred to as the “trapped layer”, may itself consist of a stack of several layers such as that described, for instance, in Document U.S. Pat. No. 5,583,725, in order to provide a so-called Synthetic Anti-Ferromagnetic (SAF) layer. Similarly, it is possible to replace each of the single storage cells of the magnetic tunnel junction by a dual magnetic tunnel junction such as that described, for example, in the Publication Y. SAITO & al, Journal of Magnetism and Magnetic Materials>>, Volume 223, 2001, page 293.
In this case, the storage layer is placed between two insulating layers with the structure comprising two reference layers positioned on the faces opposite the said respective insulating layers.
The most classic architecture, referred to as “FIMS” (Field Induced Magnetic Switching), i.e. reversal of magnetizations by an induced magnetic field, is described in Document U.S. Pat. No. 6,021,065 and in the Publication “Journal of Applied Physics” vol. 81, 1997, page 3758 and is shown in FIG. 1.
As can be seen in FIG. 1 which shows the prior art, each storage cell (10) consists of a CMOS transistor (12) associated with a magnetic tunnel junction MTJ (11). Said tunnel junction (11) comprises at least one magnetic layer (20) referred to as the “storage layer” or “free layer”, a thin insulating layer (21) and a magnetic layer (22) referred to as the “trapped layer” or “reference layer”.
The operation of these magnetic memories with storage cells each consisting of a magnetic tunnel junction involves, at the time of a write, generating an impulsive magnetic field produced by current lines or conductors associated with each of said magnetic cells.
Thus, in the context of an FIMS architecture, there are three current line levels. In FIG. 1, the two line levels (14) (Word line) and (15) (Bit line), generally arranged at 90° relative to each other, are designed to generate magnetic field pulses which make it possible to switch the magnetization of free layer (20) during the write process. These magnetic field pulses are produced by passing brief electrical pulses having a typical duration of 2 to 5 ns and an intensity of the order of several milliamps (mA) through current lines (14) and (15). The intensity of these pulses and their synchronization are adjusted so that only the magnetization of the storage cell located at the cross-point of these two current lines is capable of switching.
An additional current line level (16), also referred to as a “Control line” is designed to control opening or closing of the selection or switching transistor (12) channel associated with each storage cell in order to be able to address each storage cell individually. In other words, CMOS transistors (12) are used as switches.
When writing the memory cell in question, the selected transistor (12) is blocked or OFF and therefore no current flows through the transistor. A current pulse I is sent through the two current lines (14) and (15) which correspond to the selected storage cell (10). The amplitude of current pulse I is such that the magnetic field created is not sufficient to switch the storage cells on lines (14) or (15), except at the cross-point of lines (14) and (15) where the joint contribution of the two lines is sufficient to generate a magnetic field which is sufficient and capable of switching the magnetization of layer (20) of the storage cell in question.
In read mode, transistor (12) is in saturated mode or ON because a positive current pulse is applied to the gate of said transistor via control line (16) and the current which flows is maximal. A test current is then sent through current line (14) and this can only pass through the storage cell whose transistor (12) is in saturated mode or ON. This current is used to measure the resistance of the magnetic tunnel junction (11) of said selected storage cell (10). Compared with a reference storage cell (not shown), it is then possible to determine the corresponding state of storage cell (10)—“0” (for a configuration with parallel low-resistance magnetization) or “1” (for a configuration with antiparallel high-resistance magnetization).
From the above explanations, it is apparent that the intensity of the pulses that flow through current lines (14) and (15) and their synchronization are adjusted so that only the magnetization of the storage cell located at the cross-point of these two current lines (selected cell) can switch due to the effect of the magnetic field generated by the two conductors. The other storage cells located on the same row or same column (half-selected elements) are in fact only subjected to the magnetic field of one of the conductors (14, 15) and consequently do not reverse.
Given the nature of the mechanism for writing these storage cells, the limits of this architecture are readily apparent.
Because writing is obtained using an external magnetic field, writing is subject to the value of the individual reversal field of each storage cell. Since the distribution function of the reversal fields for all the storage cells is wide (in fact it is not uniform because of fabrication constraints and inherent statistical fluctuations), the magnetic field at the selected storage cell must exceed the highest reversal field in the statistical distribution, at the risk of inadvertently reversing certain storage cells located on the corresponding row or column, where the reversal field in the lower part of the distribution is weaker than the magnetic field generated by the row or column alone. In addition, the power consumption of a memory which uses such an external magnetic field will be higher, the wider the distribution of the reversal field.
Moreover, given the fact that, generally speaking, the average value of the reversal field increases as the size of storage cells decreases and cell size tends to decrease in order to save space, future product generations are likely to require even higher currents. Consequently, the more highly integrated these memories are, the more power they require in order to operate.
Another drawback of these prior-art memories is the stability of the magnetization of the free layer with respect to thermal fluctuations as the size of the storage cell decreases. In fact, the energy barrier that must be overcome in order to switch the magnetization of this layer from one orientation to another is proportional to the volume of this layer. As this volume reduces, the height of the barrier then becomes comparable to thermal agitation. Information written in the memory is then no longer preserved. To overcome this difficulty, one is forced to increase the magnetic anisotropy of the free layer by selecting a material with higher anisotropy or by enhancing the anisotropy of the storage cell for example. But doing this increases the magnetic field which is required in order to obtain magnetic switching and hence also increases the power consumed in order to generate the field required to obtain magnetic switching. The current in the word line and bit line may, in certain cases, even exceed the limiting threshold imposed by electromigration in these conductive lines (typically of the order of 107 A/cm2).
Also, in order to overcome this problem, the use of magnetic random-access memories, with thermally-assisted switching (TAS), often referred to by the abbreviation TAS-MRAM, in which the free layer or reference layer is itself trapped by an antiferromagnetic layer, has been proposed. This improvement is, for example, described in Document U.S. Pat. No. 6,385,082.
In this configuration, rather than achieving memory-cell write selectivity by combining two perpendicular magnetic field pulses, write selectivity is obtained by combining a brief increase in the temperature of the storage cell to be addressed, produced by a current pulse which flows through said storage cell in question, by using either a magnetic field pulse or by spin transfer obtained by passing a spin-polarised current through the storage layer of said storage cell.
Such a configuration is shown in FIG. 2. In this Figure, free layer (40) of magnetic tunnel junction (31) is trapped by antiferromagnetic layer (41). In the same way as in the case of FIMS memories, an insulating layer (42) is sandwiched between magnetic free layer (40) and magnetic layer (43) referred to as the “trapped layer”. In this configuration, the two magnetic layers are advantageously made of 3d transition metals (Fe, Co, Ni) and alloys thereof, undoped or doped (especially with boron) and the insulating layer can be made of alumina or magnesium oxide. In one advantageous version, the trapped magnetic layer (43) is coupled with antiferromagnetic layer (44), the function of which is to trap layer (43) so that its magnetization does not switch at the time of a write.
Here also, antiferromagnetic layer (44) can be a synthetic antiferromagnetic layer consisting of several layers.
In this configuration, antiferromagnetic layer (41) has a so-called “blocking” (limit) temperature TB above which the so-called stabilising “exchange” magnetic field which it exerts on layer (40) is no longer effective on free layer (40). The material of which antiferromagnetic layer (41) is made and its thickness are selected so that the blocking temperature TB exceeds the temperature at which the memory is used (standby operating temperature). Similarly, the blocking temperature TB of antiferromagnetic layer (44) adjacent to trapped layer (43) is selected so that it exceeds and is quite different to the blocking temperature of antiferromagnetic layer (41).
Thus, at temperatures below the blocking temperature of antiferromagnetic layer (41), free layer (40) is stabilised by the exchange magnetic field and it is therefore very difficult to reverse its magnetization simply by applying an external magnetic field or spin transfer obtained by passing spin-polarised current through the free layer. At the blocking temperature of antiferromagnetic layer (41) and above this temperature, because the exchange field is zero, it then becomes very easy to reverse the magnetization of free layer (40) by means of an external magnetic field, provided that the latter exceeds the coercive field strength of the free layer (40) at a given temperature or by using spin transfer by passing spin-polarised current of sufficiently high density through the free layer to cause magnetic switching. Because of this, for free layer (40), one chooses a material which allows the free layer to have a weak coercive field strength if switching is obtained by a magnetic field or a low critical switching current density if switching is obtained by spin transfer.
This particular architecture comprises two or three current line levels depending whether switching is obtained by spin transfer or by magnetic field. To obtain writing using a magnetic field, a so-called “field line” current line (30) is placed underneath magnetic tunnel junction (31) without actually being in contact with the latter. This line is intended to generate the magnetic field required in order to reverse free storage layer (40) when an electric current of several milliamps (mA) flows through it. There is no such line if switching is obtained by spin transfer. There is another current line (32) referred to as the “bit line” above magnetic tunnel junction (31) of the storage cell in question and in contact with the latter. A third current line (33), referred to as the “word line”, is in contact, through a via (34), with a CMOS transistor (35), the “word line” of which constitutes the gate. Similarly, for FIMS, the word line controls opening or closing of the transistor channel over the entire length by applying or not applying a threshold voltage, with each of the transistors operating as a switch for each of the associated storage cells.
In read mode, the CMOS transistor (35) associated with the storage cell that is to be read is closed by applying a sufficient voltage in word line (33). Bit line (32) then sends a test current which can only flow through the sole storage cell whose transistor (35) is closed (conducting). This current is used to measure the resistance of the magnetic tunnel junction (31) of the selected storage cell. The corresponding state of the storage cell—“1” or “0”—is thus determined by comparison with a reference storage cell (not shown) with the “1” state corresponding, for example, to maximum resistance and the “0” state corresponding to minimum resistance.
In write mode, the CMOS transistor (35) of the storage cell that is to be written is closed by applying a sufficient voltage in word line (33). A heating current having an intensity greater than the test current is then sent to the storage cell to be written by bit line (32). Above a certain current density, the current causes the temperature of magnetic tunnel junction (31) to rise above the blocking temperature of antiferromagnetic layer (41). The exchange field which stabilises free layer (40) then becomes zero and said free layer is then very unstable. To obtain magnetic switching using a magnetic field, an electric pulse of several milliamps (mA) having a duration of several nanoseconds is then sent through field line (30) once the blocking temperature is reached (after several nanoseconds). This pulse generates a magnetic field which is sufficient to reverse free layer (40) in the desired direction (to write a “1” or a “0” bit) because, as described above, this free layer (40) is very unstable with weak intrinsic coercivity. Once free layer (40) has been written, the electric current in field line (30) is switched off, the write magnetic field becomes zero and the heating current in magnetic tunnel junction (31) is then switched off (by switching off the current in bit line (32) and opening transistor (35)). The overall temperature of the storage cell then drops very rapidly (several nanoseconds) below the blocking temperature of antiferromagnetic layer (41) (typically to the standby operating temperature) and the exchange field then returns to its initial value and, as a result, stabilises free layer (40).
To obtain switching by spin transfer, one uses the heating current to both heat the storage layer of the tunnel junction and to apply spin transfer-torque to the magnetization of said layer. To make the magnetization of the storage layer switch, the heating-current electrons must flow from the reference layer to the storage layer and this means that the heating current must flow from the storage layer to the reference layer. Conversely, to make the magnetization of the storage layer switch to the antiparallel state, the heating-current electrons must flow from the storage layer to the reference layer and this means that the heating current must flow from the reference layer to the storage layer.
Such magnetic memories with thermally-assisted writing have a certain number of advantages which include:                considerable improvement in write selectivity because only the storage cell that is to be written is heated;        information written to the memory is preserved even when the storage cell is exposed to stray magnetic fields at ambient temperature;        improved thermal stability of information thanks to the use of materials with high magnetic anisotropy (intrinsic anisotropy and anisotropy due to the shape of the storage cell or the exchange anisotropy field of the storage layer) at ambient temperature;        possibility of significantly reducing the size of storage cells without thereby affecting their stability limit by using materials having high magnetic anisotropy at ambient temperature or having a storage layer trapped by exchange anisotropy;        reduced power consumption at the time of a write;        possibility of obtaining multi-level storage cells in certain circumstances.        
It has also been demonstrated that this technology can be used to implement logic elements such as reprogrammable logic gates (see, for example, the Publication “Evaluation of a non-volatile FPGA based on MRAM technology” by Zhao-W; Belhaire-E; Javerliac-V; Chappert-C; Dieny-B, Proceedings. 2006 International Conference on Integrated Circuit Design and Technology. 2006: 4 pp, IEEE, Piscataway, N.J., USA). These logic elements also combine CMOS semiconductor components with magnetic tunnel junctions such as the MRAMS described above. Unlike memories whose purpose is to store information, these logic elements are used to process information and to perform logic operations on information. Magnetic tunnel junctions are often used in these elements as variable resistors which make it possible to change the switching thresholds of CMOS circuits.
The object of the present invention relates to both MRAMS with thermally-assisted writing and such logic elements in which the magnetic configurations of tunnel junctions are modified by writing by using a field or spin transfer with thermal assistance.
Notwithstanding these advantages, one is nevertheless confronted with certain difficulties in terms of fabrication technology.
In the context of magnetic memories with thermally-assisted writing which use magnetic tunnel junctions having an insulating layer based on alumina, one uses an alloy based on manganese, especially IrMn and FeMn, as an antiferromagnetic layer intended to trap the storage layer. Using such a layer has no effect on the magnetoresistance ratio. This result is chiefly due to the inherently amorphous nature of the alumina which constitutes the tunnel barrier of the magnetic tunnel junction. This amorphous nature is preserved after the annealing phase required for the stack thus produced, annealing being necessary in order to give the polarising exchange field at the interface between the antiferromagnetic magnetization-trapping layer and the ferromagnetic reference layer a predefined orientation. This amorphousness has no effect on the texture of the upper antiferromagnetic layer (IrMn) for generating a high exchange anisotropy field. In fact, the magnetoresistance value of a magnetic tunnel junction based on alumina is not affected by using such an upper antiferromagnetic layer.
However, the situation is totally different if one uses magnetic tunnel junctions based on crystalline or textured magnesium oxide.
Firstly, the reader is reminded that using a magnetic tunnel junction which utilises a tunnel barrier based on magnesium oxide makes it possible to improve magnetoresistance amplitudes significantly. It has been demonstrated that this improvement is inherent in the crystal structure of the MgO tunnel barrier and the adjacent ferromagnetic layers. Both the MgO tunnel barrier and the adjacent ferromagnetic layers must be monocrystalline or highly textured with a body-centred cubic crystallographic arrangement (001) so that there can be a symmetrical spin-dependent filtering effect across the tunnel barrier. This way, one obtains magnetoresistance ratios well in excess of 100% at ambient temperature using magnetic tunnel junctions in which one uses:                body-centred cubic Fe, Co or CoFe ferromagnetic layers;        or textured junctions which include also body-centred cubic polycrystalline CoFe or Co ferromagnetic layers        or a CoFeB/MgO/CoFeB stack with deposited amorphous CoFeB.        
In the latter case, the MgO tunnel barrier grows with a highly-oriented body-centred cubic texture at the level of its interface with the lower amorphous CoFeB layer. The thermal annealing process performed after depositing the stack is required in order to bring about local recrystallisation with body-centred cubic crystal orientation of the magnetic layers which are in contact with the MgO tunnel barrier. At the same time, annealing fixes the exchange magnetic field which polarises the reference layer.
As a result of these observed differences, spin-dependent magneto-transport properties also differ, depending whether the magnetic tunnel junction is based on alumina or magnesium oxide. Spin filtering based on the symmetry of electronic wave functions which are characteristic of a textured crystal structure of the tunnel barrier and the adjacent ferromagnetic layers produces higher magnetoresistance values. This filtering is also more sensitive to structural disparities between the various layers of the stack. In the specific case of magnetic tunnel junctions with a tunnel barrier made of MgO, depositing a MgO tunnel barrier having a body-centred cubic crystal structure also involves growing an upper ferromagnetic layer with an identical crystal structure so as to ensure a high TMR value based on the effect of electrons being filtered by the tunnel barrier spin-dependently.
As stated earlier, in cases where a storage layer which is polarised by an exchange field is used for magnetic memories with thermally-assisted writing, one must deposit an antiferromagnetic layer with a low blocking temperature on the upper face of said storage layer. Usually, this antiferromagnetic layer is organised with a body-centred cubic crystal structure in order to obtain a high polarising exchange field. This being so, one comes up against the problem of crystallographic incompatibility between the two types of structures required respectively for the tunnel barrier and for the upper antiferromagnetic layer and which has negative effects on the magnetoresistance ratio and on the exchange anisotropy of the storage layer.
Because of this, one is confronted by the difficulty of achieving coexistence of the following in a trilayer stack: MgO lower ferromagnetic layer/tunnel barrier/upper magnetic layer having a high magnetoresistance ratio and body-centred cubic structure with an upper bilayer constituting the ferromagnetic/antiferromagnetic storage layers with a high exchange anisotropy field obtained with a face-centred cubic structure, even though both these entities have a different preferential crystallographic structure.
It goes without saying that, although the above discussion is based on cases involving magnetic tunnel junctions which presuppose the presence of a tunnel barrier which separates the reference layer from the storage layer, the same problems of adapting the crystallographic structures are encountered in cases where semiconductor separation layers (for instance germanium, silicon or GaAs) or metal/heterogeneous oxide separation layers such as so-called confined-current-paths layers, developed in the context of magnetoresistive read heads for hard disks, are used. The latter are prepared, for example, by oxidising thin layers of Al1-xCux alloys where x is 0.5 to 10%.